SPAKMC331CFC20中文资料恩XP数据手册PDF规格书

Introduction

The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications. The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a general-purpose timer (GPT), and a queued serial module (QSM). The MCU can either synthesize an internal clock signal from an external reference or use an external clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum system clock speed is 20.97 MHz. Because MCU operation is fully static, register and memory contents are not affected by a loss of clock. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability.

特性 Features

• Modular Architecture

• Central Processing Unit (CPU32)

— Upward Object Code Compatible

— New Instructions for Controller Applications

— 32-Bit Architecture

— Virtual Memory Implementation

— Loop Mode of Instruction Execution

— Table Lookup and Interpolate Instruction

— Improved Exception Handling for Controller Applications

— Trace on Change of Flow

— Hardware Breakpoint Signal, Background Mode

— Fully Static Operation

• System Integration Module (SIM)

— External Bus Support

— Programmable Chip-Select Outputs

— System Protection Logic

— Watchdog Timer, Clock Monitor, and Bus Monitor

— System Protection Logic

— System Clock Based on 32.768-kHz Crystal for Low Power Operation

— Test/Debug Submodule for Factory/User Test and Development

• Queued Serial Module (QSM)

— Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmitter

(UART): Modulus Baud Rate, Parity

— Queued Serial Peripheral Interface (QSPI): 80-Byte RAM, Up to 16 Automatic Transfers

— Dual Function I/O Ports

— Continuous Cycling, 8 to 16 Bits per Transfer

• General-Purpose Timer (GPT)

— Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler

— Three Input Capture Channels

— Four Output Compare Channels

— One Input Capture/Output Compare Channel

— One Pulse Accumulator/Event Counter Input

— Two Pulse-Width Modulation Outputs

— Optional External Clock Input