SP8852E中文资料ZARLINK数据手册PDF规格书

The SP8852E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other parts in the series are the SP8854E which has hard wired reference counter programming and requires only a single 16-bit programming word, and the SP8855E which is fully programmable using hard wired links or switches.

The SP8852E is programmed using a 16-bit parallel data bus. Data can be stored in one of two internal buffers, selected by a single address bit on the input interface. In order to fully program the device, two 16-bit words are required, one to select the RF division ratio (A and M counters) and phase detector gain, and one to set the 10-bit reference divider count, phase detector state and sense. Once the reference divide ratio has been set, frequency changes can be made by a single 16-bit data load entry to the RF divider chain.

FEATURES

■ 2·7 GHz Operating Frequency

■ Single 5V Supply

■ Low Power Consumption <1·3W

■ High Comparison Frequency : 20MHz

■ High Gain Phase Detector : 1mA/rad

■ Zero ‘Dead Band’ Phase Detector

■ Wide Range of RF and Reference Division Ratios

■ Programming by Dual Word Data Transfer