SNJ54LS674FK.A中文资料德州仪器数据手册PDF规格书

Ls673

16.Bic Serial in, Serial Out Shift

Rogistor with 16.81 Paral Out.

Storage Register

= Performs Seriskto-Parallel Conversion

LS674

16.Bit Parallobin, SorialOut

Shift Ragistor

Parforms Paralek-o-Serial Conversion

description

SNBALSG73, SN7ALS673

The 'LS673 is a 16-bit shift register and a 16-bit storage

register in a single 24-pin package. A three-state

input/output (SER/Q15) port to the shit register allows

serial entry and/or reading of data. The storage register

is connected in a parallel data I00p with the shift register

and may be asynchronously cleared by taking the store-

clear input low. The storage register may be parallel

loaded with shift-register data to provide shift-register

status via the parallel outputs. The shift register can be

parallel loaded with the storage-register data upon com-

mand.

A high logic level at the chip-level (CS) input disables

both the shiftregister clock and the storage register

clock and places SER/Q1S in the high-impedance state.

The store-clear function is not disabled by the chip

select.

Caution must be exercised to prevent false clocking of

either the shift register or the storage register via the

chip-select input. The shift clock should be low during

the low-to-high transition of chip select and the store

clock should be low during the high-to-low transition of

chip select.

‘SNSALS674, SN7ALS674

The 'LS674 is a 16-bit parallebin, seriak-out shift

register. A three-state input/output (SER/Q1S) port

provides access for entering a serial data or reading the

shift-register word in a recirculating 00p.

‘The device has four basic modes of operation:

1) Hold (do nothing)

2) Write (serially via input/output)

3) Read (serially)

4) Load (parallel via data inputs)

Low-to-high-level changes at the chip select input

should be made only when the clock input is low to pre-

vent false clocking.