OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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德州仪器

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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TI

德州仪器

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：288.18 Kbytes 页数：14 Pages

TI

德州仪器

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

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TI

德州仪器