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SN75LVDS86ADGGRG4.A中文资料德州仪器数据手册PDF规格书

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厂商型号

SN75LVDS86ADGGRG4.A

功能描述

FlatLink™ RECEIVER

丝印标识

SN75LVDS86A

封装外壳

TSSOP

文件大小

518.549 Kbytes

页面数量

22

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-11-15 20:00:00

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SN75LVDS86ADGGRG4.A规格书详情

3:21 Data Channel Expansion at up to

178.5 Mbytes/s Throughput

Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

Three Data Channels and Clock

Low-Voltage Differential Channels In and

21 Data and Clock Low-Voltage TTL

Channels Out

Operates From a Single 3.3-V Supply

Tolerates 4-kV HBM ESD

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal

Pitch

Consumes Less Than 1 mW When Disabled

Wide Phase-Lock Input Frequency Range

of 31 MHz to 68 MHz

No External Components Required for PLL

Inputs Meet or Exceed the Standard

Requirements of ANSI EIA/TIA-644

Standard

Improved Replacement for the DS90C364

and SN75LVDS86

Improved Jitter Tolerance

See SN65LVDS86A-Q1 Data Sheet for

Information About the Automotive

Qualified Version

description

The SN65LVDS86A/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers

and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions

allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over

four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data

at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input

clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. The

’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The

data bus appears the same at the input to the transmitter and output of the receiver with the data transmission

transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)

active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level

on this signal clears all internal registers to a low level.

The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0C to 70C. The

SN65LVDS86A is characterized for operation over the full Automotive temperature range of −40°C to 125°C.

供应商 型号 品牌 批号 封装 库存 备注 价格
TI/德州仪器
24+
NA/
3586
原厂直销,现货供应,账期支持!
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22+
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25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
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TI
23+
TSSOP
8560
受权代理!全新原装现货特价热卖!
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TI/德州仪器
21+
TSSOP48
36680
只做原装,质量保证
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TI/德州仪器
23+
TSSOP48
18204
原装正品代理渠道价格优势
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TI
24+
TSSOP56
95
散新!现货
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2016+
TSSOP48
3000
主营TI,绝对原装,假一赔十,可开17%增值税发票!
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TI/德州仪器
2023+
TSSOP48
6893
专注全新正品,优势现货供应
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