SN75LVDS82中文资料FlatLink™ 接收器数据手册TI规格书

描述 Description

The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS83B, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 for 21-bit transfers.When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user.The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level and places the TTL outputs in a high-impedance state.The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.

特性 Features

• 4:28 Data Channel Expansion at up to 1904 Mbps Throughput
• Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
• Four Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply With 250 mW (Typical)
• 5-V Tolerant SHTDN Input
• Falling Clock-Edge-Triggered Outputs
• Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Pixel Clock Frequency Range of 31 MHz to 68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard