25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes S

文件：483.66 Kbytes 页数：21 Pages

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

文件：389.83 Kbytes 页数：14 Pages

TI

德州仪器

具有 SSTL_18 输入和输出的 500MHz、25 位可配置寄存缓冲器

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.\n\n • Member of the Texas Instruments Widebus+™ Family\n• Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer\n• Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line\n• Differential Clock (CLK and CLK\\) Inputs\n• RESET\\ Input Disables Differential Input Receivers, Res;

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes S

文件：483.66 Kbytes 页数：21 Pages

TI

德州仪器

丝印：SU864；Package：NFBGA；25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes S

文件：483.66 Kbytes 页数：21 Pages

TI

德州仪器

丝印：SU864；Package：NFBGA；25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes S

文件：483.66 Kbytes 页数：21 Pages

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

文件：567.8 Kbytes 页数：20 Pages

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS

文件：304.96 Kbytes 页数：18 Pages

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS

文件：304.96 Kbytes 页数：18 Pages

TI

德州仪器

25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS

文件：304.96 Kbytes 页数：18 Pages

TI

德州仪器