QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS

文件：249.42 Kbytes 页数：7 Pages

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德州仪器

4 通道、2 输入、4.75V 至 5.25V 双极与非门

These devices contain four independent 2-input NAND buffer gates. The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C.   • Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

TI

德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：S373；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：S373；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SN74S373N；Package：PDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：S374；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：S374；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SN74S374N；Package：PDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器