SN74LVTH18652APM集成电路（IC）的专用逻辑器件规格书PDF中文资料

SN74LVTH18652APM属于集成电路（IC）的专用逻辑器件。由德州仪器制造生产的SN74LVTH18652APM专用逻辑器件专用逻辑 IC 设计提供应用特定的逻辑输出类型，例如 BCD 速率倍增、可寻址扫描端口、总线终端阵列、CML 驱动器、比较器、ABT 扫描测试、二进制全加法器、互补对加逆变器、可配置缓冲器、触点颤动消除器、晶体振荡器、延迟元件、差分接收器、LVTTL 到 GTLP 收发器、存储器解码器、电源良好检测器和分频器。

Members of the Texas Instruments

SCOPE E Family of Testability Products

Members of the Texas Instruments

WidebusE Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Include D-Type Flip-Flops and Control

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

B-Port Outputs of ’LVTH182652A Devices

Have Equivalent 25-W Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

description

The ’LVTH18652A and ’LVTH182652A scan test devices with 18-bit bus transceivers and registers are

members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices

supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan

access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed

transmission of data directly from the input bus or from the internal registers. They can be used either as two

9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot

samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating

the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers

and registers.

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and

output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated

registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation

to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus

(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the

high-impedance state.

Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since

the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state

when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed

with the ’LVTH18652A and ’LVTH182652A.

In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of ’LVTH182652A, which are designed to source or sink up to 12 mA, include equivalent 25-W

series resistors to reduce overshoot and undershoot.

The SN54LVTH18652A and SN54LVTH182652A are characterized for operation over the full military

temperature range of –55°C to 125°C. The SN74LVTH18652A and SN74LVTH182652A are characterized for

operation from –40°C to 85°C.