SN74LVTH18646APMG4.B中文资料德州仪器数据手册PDF规格书

Members of the Texas Instruments

SCOPE E Family of Testability Products

Members of the Texas Instruments

WidebusE Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Include D-Type Flip-Flops and Control

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

B-Port Outputs of ’LVTH182646A Devices

Have Equivalent 25-W Series Resistors, So

No External Resistors Are Required

Compatible With IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

description

The ’LVTH18646A and ’LVTH182646A scan test devices with 18-bit bus transceivers and registers are

members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices

supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan

access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed

transmission of data directly from the input bus or from the internal registers. They can be used either as two

9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot

samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating

the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers

and registers.

Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the

transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR

is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating

both buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is

clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data

is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for

presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB

and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed

with the ’LVTH18646A and ’LVTH182646A.