SN74LVTH16646DGGR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74LVTH16646DGGR属于集成电路（IC）的缓冲器驱动器接收器收发器。由德州仪器制造生产的SN74LVTH16646DGGR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

Members of the Texas Instruments

Widebus Family

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

Ioff and Power-Up 3-State Support Hot

Insertion

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flowthrough Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

The ’LVTH16646 devices are 16-bit bus

transceivers and registers designed for

low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V

system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked

into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the ’LVTH16646

devices.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both. The

select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry

used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition

between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation

mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.