SN74LVCH16T245DGVR集成电路（IC）的转换器电平移位器规格书PDF中文资料

SN74LVCH16T245DGVR属于集成电路（IC）的转换器电平移位器。由美国德州仪器公司制造生产的SN74LVCH16T245DGVR转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。

1 Features

1• Control Inputs VIH/VIL Levels are Referenced to

V CCA Voltage

• VCC Isolation Feature – If Either VCC Input is at

GND, All Outputs are in the High-Impedance State

• Overvoltage-Tolerant Inputs and Outputs Allow

Mixed-Voltage-Mode Data Communications

• Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.65 V to 5.5 V

Power-Supply Range

• Bus Hold on Data Inputs Eliminates the Need for

External Pullup and Pulldown Resistors

• Ioff Supports Partial-Power-Down Mode Operation

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

2 Applications

• Personal Electronics

• Industrial

• Enterprise

• Telecom

3 Description

This 16-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The A port

is designed to track VCCA. VCCA accepts any supply

voltage from 1.65 V to 5.5 V. The B port is designed

to track VCCB. VCCB accepts any supply voltage from

1.65 V to 5.5 V. This allows for universal low-voltage

bidirectional translation between any of the 1.8-V,

2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVCH16T245 device control pins (1DIR,

2DIR, 1OE, and 2OE) are supplied by VCCA.

The SN74LVCH16T245 device is designed for

asynchronous communication between two data

buses. The logic levels of the direction-control (DIR)

input and the output-enable (OE) input activate either

the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated, and from the B

bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW

level applied to prevent excess ICC and ICCZ.