SN74LVCH16952ADLR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74LVCH16952ADLR属于集成电路（IC）的缓冲器驱动器接收器收发器。由德州仪器制造生产的SN74LVCH16952ADLR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Operates From 1.65 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 6.6 ns at 3.3 V

· Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage

With 3.3-V VCC)

· Ioff Supports Partial-Power-Down Mode

Operation

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit registered transceiver is designed for

1.65-V to 3.6-V VCC operation.

The SN74LVCH16952A contains two sets of D-type

flip-flops for temporary storage of data flowing in

either direction. The device can be used as two 8-bit

transceivers or one 16-bit transceiver. Data on the A

or B bus is stored in the registers on the low-to-high

transition of the clock (CLKAB or CLKBA) input,

provided that the clock-enable (CEAB or CEBA) input

is low. Taking the output-enable (OEAB or OEBA)

input low accesses the data on either port.