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SN74LVCE161284DLR.A中文资料德州仪器数据手册PDF规格书

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厂商型号

SN74LVCE161284DLR.A

功能描述

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

丝印标识

LVCE161284

封装外壳

SSOP

文件大小

470.41 Kbytes

页面数量

18

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-10-12 22:59:00

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SN74LVCE161284DLR.A规格书详情

FEATURES

· Auto-Power-Up Feature Prevents Printer

Errors When Printer Is Turned On, But No

Valid Signal Is at A9–A13 Pins

· 1.4-kW Pullup Resistors Integrated on All

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

· Designed for IEEE Std 1284-I (Level-1 Type)

and IEEE Std 1284-II (Level-2 Type) Electrical

Specifications

· Flow-Through Architecture Optimizes PCB

Layout

· Ioff and Power-Up 3-State Support Hot

Insertion

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection

– ±4 kV – Human-Body Model

– ±8 kV – IEC 61000-4-2, Contact Discharge

(Connector Pins)

– ±15 kV – IEC 61000-4-2, Air-Gap Discharge

(Connector Pins)

– ±15 kV – Human-Body Model

(Connector Pins)

DESCRIPTION/ORDERING INFORMATION

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way

communication between data buses. The control-function implementation minimizes external timing

requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR)

is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and

four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive

the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a

totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements

as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface

specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have

a 1.4-kW integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high.

When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated

inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting

the BUSY signal in the cable at power on.

供应商 型号 品牌 批号 封装 库存 备注 价格
TI/德州仪器
24+
NA/
3850
原厂直销,现货供应,账期支持!
询价
TI
25+23+
TSSOP48
12055
绝对原装正品全新进口深圳现货
询价
TI
25+
TVSOP48
4500
全新原装、诚信经营、公司现货销售!
询价
TI
2025+
TVSOP-48
16000
原装优势绝对有货
询价
TI
24+
TVSOP48
1128
询价
TI/德州仪器
24+
TSSOP48
9600
原装现货,优势供应,支持实单!
询价
TexasInstruments
18+
ICIEEESTD1284TXRX48-TVSO
6800
公司原装现货/欢迎来电咨询!
询价
TI/德州仪器
2447
SS0P
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
TI
21+
TSSOP48
1574
询价
TI/德州仪器
22+
SS0P
20000
原装现货,实单支持
询价