丝印：C255；Package：SOT-23；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

丝印：C225；Package：SOT23-5；Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

文件：695.5 Kbytes 页数：10 Pages

UMW

友台半导体

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

丝印：C255；Package：SOT-23；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

丝印：CMF；Package：SC70；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

丝印：CM5；Package：SC70；SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器

丝印：CM5；Package：SC70-5；Designed for 1.65V to 5.5V VCC Operation

General Description The SN74LVC1G125 is a high performance non−inverting buffer operating from a 1.65V to 5.5V supply. This device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive. Features ● Designed for 1.65V to 5.5V VCC Operation ● Overvol

文件：695.5 Kbytes 页数：10 Pages

UMW

友台半导体

SN74LVC1G125 Single Bus Buffer Gate With 3-State Output

1 Features 1• Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max t pd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff S

文件：2.54285 Mbytes 页数：45 Pages

TI

德州仪器