SN74LVC1G125-EP中文资料具有三态输出的增强型产品单路 1.65V 至 5.5V 缓冲器数据手册TI规格书

描述 Description

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Controlled Baseline
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Qualification Pedigree
• Supports 5-V VCC Operation
• Max tpd of 3.7 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• 2000-V Human-Body Model (A114-A)
• 1000-V Charged-Device Model (C101)


Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.