DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：137.13 Kbytes 页数：7 Pages

TI

德州仪器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：148.98 Kbytes 页数：8 Pages

TI

德州仪器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：148.98 Kbytes 页数：8 Pages

TI

德州仪器

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

文件：125.21 Kbytes 页数：12 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

文件：251.4 Kbytes 页数：15 Pages

NEXPERIA

安世

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：444.43 Kbytes 页数：16 Pages

TI

德州仪器