SN74LV573ATPWR.A中文资料德州仪器数据手册PDF规格书

FEATURES

· Inputs Are TTL-Voltage Compatible

· 4.5-V to 5.5-V V CC Operation

· Typical tpd = 5.1 ns at 5 V

· Typical V OLP (Output Ground Bounce)

<0.8 V at VCC = 5 V, TA = 25°C

· Typical V OHV (Output VOH Undershoot)

>2.3 V at VCC = 5 V, TA = 25°C

· Supports Mixed-Mode Voltage Operation on

All Ports

· Ioff Supports Partial-Power-Down Mode

Operation

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs

follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.