SN74LV573ATDGVR集成电路（IC）的锁存器规格书PDF中文资料

SN74LV573ATDGVR属于集成电路（IC）的锁存器。由美国德州仪器公司制造生产的SN74LV573ATDGVR锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。

FEATURES

· Inputs Are TTL-Voltage Compatible

· 4.5-V to 5.5-V V CC Operation

· Typical tpd = 5.1 ns at 5 V

· Typical V OLP (Output Ground Bounce)

<0.8 V at VCC = 5 V, TA = 25°C

· Typical V OHV (Output VOH Undershoot)

>2.3 V at VCC = 5 V, TA = 25°C

· Supports Mixed-Mode Voltage Operation on

All Ports

· Ioff Supports Partial-Power-Down Mode

Operation

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LV573AT is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs

follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.