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SN74LV2T74中文资料德州仪器数据手册PDF规格书

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厂商型号

SN74LV2T74

功能描述

SN74LV2T74-Q1 Automotive Dual D-Type Flip-Flop With Integrated Translation

文件大小

1.66952 Mbytes

页面数量

30

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-11-15 15:17:00

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SN74LV2T74规格书详情

1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1: -40°C to +125°C

– Device HBM ESD classification level 2

– Device CDM ESD classification level C4B

• Available in wettable flank QFN (WBQA) package

• Wide operating range of 1.8 V to 5.5 V

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2 V to 1.8 V

• 1.5 V to 2.5 V

• 1.8 V to 3.3 V

• 3.3 V to 5.0 V

– Down translation:

• 5.0 V, 3.3 V, 2.5 V to 1.8 V

• 5.0 V, 3.3 V to 2.5 V

• 5.0 V to 3.3 V

• 5.5-V tolerant input pins

• Supports standard pinouts

• Up to 150 Mbps with 5-V or 3.3-V VCC

• Latch-up performance exceeds 250 mA

per JESD 17

2 Applications

• Convert a momentary switch to a toggle switch

• Hold a signal during controller reset

• Input slow edge-rate signals

• Operate in noisy environments

• Divide a clock signal by two

3 Description

The SN74LV2T74-Q1 contains two independent Dtype

positive-edge-triggered flip-flops. A low level at

the preset (PRE) input sets the output high. A low

level at the clear (CLR) input resets the output low.

Preset and clear functions are asynchronous and not

dependent on the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data

(D) input meeting the setup time requirements is

transferred to the outputs (Q, Q) on the positive-going

edge of the clock (CLK) pulse. Clock triggering occurs

at a voltage level and is not directly related to the

rise time of the input clock (CLK) signal. Following

the hold-time interval, data at the data (D) input can

be changed without affecting the levels at the outputs

(Q, Q). The output level is referenced to the supply

voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and

5-V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). In addition, the 5-V tolerant input pins

enable down translation (for example, 3.3 V to 2.5 V

output).

供应商 型号 品牌 批号 封装 库存 备注 价格
TI/德州仪器
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
询价
TexasInstruments
18+
ICQUAD2-INPUTORGATE14-SO
6800
公司原装现货/欢迎来电咨询!
询价
1000
原装正品
询价
TI/德州仪器
2447
TSSOP14
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
TI德州仪器
22+
24000
原装正品现货,实单可谈,量大价优
询价
TI/德州仪器
25+
原厂封装
10280
询价
TI
23+
N/A
8000
只做原装现货
询价
TI
23+
N/A
7000
询价
TI/德州仪器
22+
TSSOP
20000
原装现货,实单支持
询价
TI
24+
TSSOP
70
只做原装,欢迎询价,量大价优
询价