SN74LV273A集成电路（IC）的触发器规格书PDF中文资料

SN74LV273A属于集成电路（IC）的触发器。由德州仪器制造生产的SN74LV273A触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1:

• 40°C to + 125°C, TA

– Device HBM ESD Classifiaction Level 2

– Device CDM ESD Classifcation Level C6

• Available in wettable flank QFN (WRKS) package

• 2 V to 5.5 V VCC operation

• Maximum tpd of 10.5 ns at 5 V

• Supports mixed-mode voltage operation on all

ports

• Ioff supports partial-power-down mode operation

• Latch-up performance exceeds 250 mA per JESD

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2 Applications

• Synchronize digital signals to clock

• Use fewer inputs to monitor signals

• Convert a switch to a toggle

3 Description

The SN74LV273A-Q1 device is an octal positive-edge

triggered D-type flip-flop with shared direct active low

clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup

time requirements is transferred to the (Q) outputs

on the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not related directly to the transition time of

the positive-going pulse. When CLK is at either the

high or low level or transitioning from a high level

to a low level, the D input has no effect at the

output. Information at the data (Q) outputs can be

asynchronously cleared with a low level input through

the clear (CLR) pin.