丝印：LV165BEP；Package：TSSOP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

文件：850.08 Kbytes 页数：25 Pages

TI

德州仪器

丝印：LV165BEP；Package：TSSOP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

文件：850.27 Kbytes 页数：25 Pages

TI

德州仪器

丝印：LV165BEP；Package：TSSOP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

文件：814.61 Kbytes 页数：24 Pages

TI

德州仪器

丝印：LV165BEP；Package：TSSOP；SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, Parallel-Load 8-Bit Shift Registers

1 Features • 2 V to 5.5 V VCC operation • Maximum tpd of 10.5 ns at 5 V • Supports mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 • Operating ambient temperature: -55°C to +125°C • Supports defe

文件：814.61 Kbytes 页数：24 Pages

TI

德州仪器