SN74LV165A-EP中文资料德州仪器数据手册PDF规格书

1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1:

• 40°C to + 125°C, TA

– Device HBM ESD Classifiaction Level 2

– Device CDM ESD Classifcation Level C6

• Available in wettable flank QFN (WBQB) package

• 2 V to 5.5 V VCC operation

• Maximum tpd of 10.5 ns at 5 V

• Supports mixed-mode voltage operation on all

ports

• Ioff supports partial-power-down mode operation

• Latch-up performance exceeds 250 mA per JESD

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2 Applications

• Increase the number of inputs on a microcontroller

3 Description

The SN74LV165A-Q1 device is a parallel-load, 8-bit

shift registers designed for 2 V to 5.5 V VCC operation.

When the device is clocked, data is shifted toward the

serial output QH. Parallel-in access to each stage is

provided by eight individual direct data inputs that are

enabled by a low level at the shift/load (SH/ LD) input.

The SN74LV165A-Q1 devices features a clock-inhibit

function and a complemented serial output, Q H.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs, preventing damaging current backflow

through the devices when they are powered down.