SN74LS113AD技术资料参数行情报价德州仪器-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
SN74LS113AD	文件：259.97 Kbytes Page：6 Pages	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes 页数：6 Pages	TI 德州仪器	TI
SN74LS113AN	文件：259.97 Kbytes Page：6 Pages	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes 页数：6 Pages	TI 德州仪器	TI
SN74LS113D	文件：140.23 Kbytes Page：4 Pages	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha 文件：140.23 Kbytes 页数：4 Pages	MOTOROLA 摩托罗拉	MOTOROLA
SN74LS113N	文件：140.23 Kbytes Page：4 Pages	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha 文件：140.23 Kbytes 页数：4 Pages	MOTOROLA 摩托罗拉	MOTOROLA

更多SN74LS113AD供应商更新时间2026-1-29 10:46:00