SN74HCS596-Q1数据手册TI中文资料规格书

描述 Description

The SN74HCS596-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

特性 Features

• AEC-Q100 Qualified for automotive applications:
• Device temperature grade 1: –40°C to +125°C, TA
• Device HBM ESD Classification Level 2
• Device CDM ESD Classifcation Level C6

• Wide operating voltage range: 2 V to 6 V
• Schmitt-trigger inputs allow for slow or noisy input signals
• Low power consumption
• Typical ICC of 100 nA
• Typical input leakage current of ±100 nA

• ±7.8-mA output drive at 6 V