DUAL J.K FLOPS WITH CLEAR

文件：123.49 Kbytes 页数：4 Pages

TI

德州仪器

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

文件：52.09 Kbytes 页数：7 Pages

PHI

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

文件：245.37 Kbytes 页数：13 Pages

NEXPERIA

安世

SSOP-14

TI/德州仪器

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NA

TI

德州仪器

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