SN74HC193DR集成电路（IC）的计数器除法器规格书PDF中文资料

SN74HC193DR属于集成电路（IC）的计数器除法器。由德州仪器制造生产的SN74HC193DR计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-μA Max ICC

Typical tpd = 20 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 μA Max

Look-Ahead Circuitry Enhances Cascaded

Counters

Fully Synchronous in Count Modes

Parallel Asynchronous Load for Modulo-N

Count Lengths

Asynchronous Clear

description/ordering information

The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change

coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the

output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP

or DOWN). The direction of counting is determined by which count input is pulsed while the other count input

is high.

All four counters are fully programmable; that is, each output may be preset to either level by placing a low on

the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the

data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers

simply by modifying the count length with the preset inputs.

A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The

clear function is independent of the count and LOAD inputs.

These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output

produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)

output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can

be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.