SN74HC139-Q1中文资料德州仪器数据手册PDF规格书

Qualified for Automotive Applications

Targeted Specifically for High-Speed

Memory Decoders and Data-Transmission

Systems

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive up to Ten LSTTL Loads

Low Power Consumption, 80-μA Max ICC

Typical tpd = 10 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 μA Max

Incorporate Two Enable Inputs to Simplify

Cascading and/or Data Reception

ESD Protection Level per AEC-Q100

Classification

− 2000-V (H2) Human-Body Model

− 200-V (M3) Machine Model

− 1000-V (C5) Charged-Device Model

description/ordering information

The SN74HC139 device is designed for

high-performance memory-decoding or data-routing

applications requiring very short propagation delay

times. In high-performance memory systems, this

decoder can minimize the effects of system

decoding. When employed with high-speed

memories utilizing a fast enable circuit, the delay time

of this decoder and the enable time of the memory

usually are less than the typical access time of the

memory. This means that the effective system delay

introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low

enable (G) input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features

fully buffered inputs, each of which represents only one normalized load to its driving circuit.