SN74GTLPH1655集成电路（IC）的通用总线功能规格书PDF中文资料

SN74GTLPH1655属于集成电路（IC）的通用总线功能。由德州仪器制造生产的SN74GTLPH1655通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。

FEATURES

· Member of Texas Instruments' Widebus™

Family

· UBT™ Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, or Clocked Modes

· TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

· OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

· Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

· Partitioned as Two 8-Bit Transceivers With

Individual Latch Timing and Output Control,

but With a Common Clock

· LVTTL Interfaces Are 5-V Tolerant

· High-Drive GTLP Outputs (100 mA)

· LVTTL Outputs (–24 mA/24 mA)

· Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

Data-Transfer Rate and Signal Integrity in

Distributed Loads

· Ioff, Power-Up 3-State, and BIAS VCC Support

Live Insertion

· Bus Hold on A-Port Data Inputs

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION

The SN74GTLPH1655 is a high-drive, 16-bit UBT™ transceiver that provides LVTTL-to-GTLP and

GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent,

latched, and clocked modes of data transfer. The device provides a high-speed interface between cards

operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times

faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing

(<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry.

Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using

several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with

equivalent load impedance down to 11 W.

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard

JESD 8-3. The ac specification of the SN74GTLPH1655 is given only at the preferred higher noise-margin GTLP,

but the user has the flexibility of using this device at either GTL

VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input

reference voltage.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output

connections, preventing disturbance of active data on the backplane during card insertion or removal, and

permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated

backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal

integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC

input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to

optimize system data-transfer rate and signal integrity to the backplane load.

Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or

pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.