8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provid

文件：1.05473 Mbytes 页数：23 Pages

TI

德州仪器

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

文件：645.69 Kbytes 页数：21 Pages

TI

德州仪器

具有独立 LVTTL 端口和反馈路径的 8 位 LVTTL-GTLP 可调节边沿速率寄存收发器

The SN74GTLP22033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provide • Member of the Texas Instruments Widebus™ Family\n• OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference\n• Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring\n• LVTTL Interfaces Are 5-V Tolerant\n• Reduced LVTTL Outputs (-12 mA/12 mA)\n• I;

TI

德州仪器

丝印：GTLP22033；Package：TSSOP；8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provid

文件：1.05473 Mbytes 页数：23 Pages

TI

德州仪器

丝印：GTLP22033；Package：TSSOP；8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provid

文件：1.05473 Mbytes 页数：23 Pages

TI

德州仪器

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provid

文件：1.05473 Mbytes 页数：23 Pages

TI

德州仪器

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provid

文件：1.05473 Mbytes 页数：23 Pages

TI

德州仪器

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

文件：645.69 Kbytes 页数：21 Pages

TI

德州仪器

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

文件：645.69 Kbytes 页数：21 Pages

TI

德州仪器

Package：48-TFSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 专用逻辑器件 描述：IC REG TXRX LVTTL-GTLP 48-TVSOP

TI

德州仪器