SN74CBT16811C中文资料具有预充电输出和 –2V 下冲保护的 5V、1:1 (SPST)、24 通道 FET 总线开关数据手册TI规格书

描述 Description

The SN74CBT16811C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16811C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBT16811C is organized as two 12-bit bus switches with separate output-enable (1OE\\, 2OE\\) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE\\ is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\\ is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to BIASV through the equivalent of a 10-k resistor when OE\\ is high, or if the device is powered down (VCC = 0 V).

During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Member of the Texas Instruments Widebus™ Family
• B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical)
• Low Power Consumption (ICC = 3 µA Max)
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Ioff Supports Partial-Power-Down Mode Operation
• ESD Performance Tested Per JESD 22
• 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating
Widebus is a trademark of Texas Instruments.