SN74CB3T3384中文资料具有 2 个控制输入和电平转换器的 3.3V、1:1 (SPST)、10 通道通用 FET 总线开关数据手册TI规格书

描述 Description

The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3384 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).

The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE\\, 2OE\\) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\\ is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\\ is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3384 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).

The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE\\, 2OE\\) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\\ is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\\ is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Output Voltage Translation Tracks VCC
• 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC
• 5-V-Tolerant I/Os With Device Powered-Up or Powered-Down
• Low ON-State Resistance (ron) Characteristics (ron = 5 Typical)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• VCC Operating Range From 2.3 V to 3.6 V
• Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• 2000-V Human-Body Model (A114-B, Class II)
• Supports Digital Applications: Level Translation, Memory Interleaving, Bus Isolation
• Ideal for Low-Power Portable Equipment