SN74BCT573DW.A中文资料德州仪器数据手册PDF规格书

Operating Voltage Range of 4.5 V to 5.5 V

State-of-the-Art BiCMOS Design

Significantly Reduces ICCZ

Full Parallel Access for Loading

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is

high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched

at the logic levels that were set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.