SN74AUP2G08RSER.B中文资料德州仪器数据手册PDF规格书

1 Features

• Wide operating VCC range of 0.8V to 3.6V

• Low static-power consumption

(ICC = 0.9μA max)

• Low dynamic-power consumption

(Cpd = 4.3pF typ at 3.3V)

• Low noise – overshoot and undershoot

<10% of VCC

• Ioff supports partial-power-down mode operation

• Schmitt-trigger action allows slow input transition

and better switching noise immunity at the input

(Vhys = 250mV Typ at 3.3V)

• 3.6V I/O tolerant to support mixed-mode signal

operation

• tpd = 5.9ns max at 3.3V

• Latch-up performance exceeds 100mA per JESD

78, Class II

2 Applications

• Combine power good signals

• Combine enable signals

3 Description

This dual 2-input positive-AND gate is designed for

0.8V to 3.6V VCC operation and performs the Boolean

function Y = A ● B in positive logic.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs when VCC = 0V, preventing damaging current

backflow through the device when it is powered down.