LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-OR GATE

1FEATURES • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at V CC = 2.5 V) – 3.3 V to 2.5 V (at V CC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Ou

文件：520.65 Kbytes 页数：18 Pages

TI

德州仪器

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-OR GATE

1FEATURES • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at V CC = 2.5 V) – 3.3 V to 2.5 V (at V CC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Ou

文件：520.9 Kbytes 页数：18 Pages

TI

德州仪器

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-OR GATE

文件：173.79 Kbytes 页数：11 Pages

TI

德州仪器

Low-power 2-input EXCLUSIVE-OR gate with voltage-level translator

1. General description The 74AUP1T86 provides the single 2-input EXCLUSIVE-OR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T86 is designed for logic-level translation applications with input switching le

文件：236.49 Kbytes 页数：14 Pages

NEXPERIA

安世

Low-power 2-input EXCLUSIVE-OR gate with voltage-level translator

1. General description The 74AUP1T86 provides the single 2-input EXCLUSIVE-OR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T86 is designed for logic-level translation applications with input switching le

文件：236.49 Kbytes 页数：14 Pages

NEXPERIA

安世

Low-power 2-input EXCLUSIVE-OR gate with voltage-level translator

1. General description The 74AUP1T86 provides the single 2-input EXCLUSIVE-OR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T86 is designed for logic-level translation applications with input switching le

文件：236.49 Kbytes 页数：14 Pages

NEXPERIA

安世