SN74AUP1G02DRLR.B中文资料德州仪器数据手册PDF规格书

1 Features

1• Available in the Ultra Small 0.64 mm2 Package

(DPW) with 0.5-mm Pitch

• Low Static-Power Consumption

(ICC = 0.9 μA Max)

• Low Dynamic-Power Consumption

(Cpd = 4.3 pF Typ at 3.3 V)

• Low Input Capacitance (Ci = 1.5 pF Typ)

• Low Noise – Overshoot and Undershoot

<10% of VCC

• Ioff Supports Live Insertion, Partial-Power-Down

Mode, and Back-Drive Protection

• Input Hysteresis Allows Slow Input Transition and

Better Switching-Noise Immunity at the Input

(Vhys = 250 mV Typ at 3.3 V)

• Wide Operating VCC Range of 0.8 V to 3.6 V

• Optimized for 3.3-V Operation

• 3.6-V I/O Tolerant to Support Mixed-Mode Signal

Operation

• tpd = 4.6 ns Max at 3.3 V

• Suitable for Point-to-Point Applications

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

2 Applications

• ATCA Solutions

• Active Noise Cancellation (ANC)

• Barcode Scanner

• Blood Pressure Monitor

• CPAP Machine

• Cable Solutions

• DLP 3D Machine Vision, Hyperspectral Imaging,

Optical Networking, and Spectroscopy

• E-Book

• Embedded PC

• Field Transmitter: Temperature or Pressure

Sensor

• Fingerprint Biometrics

• HVAC: Heating, Ventilating, and Air Conditioning

• Network-Attached Storage (NAS)

• Server Motherboard and PSU

• Software Defined Radio (SDR)

• TV: High-Definition (HDTV), LCD, and Digital

• Video Communications System

• Wireless Data Access Card, Headset, Keyboard,

Mouse, and LAN Card

• X-ray: Baggage Scanner, Medical, and Dental

3 Description

This single 2-input positive-NOR gate performs the

Boolean function Y = A + B or Y = A × B in positive

logic.