SN74AUC2G125中文资料具有三态输出的 2 通道、0.8V 至 2.7V 高速缓冲器数据手册TI规格书

描述 Description

This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

特性 Features

• Available in the Texas Instruments NanoFree™ Package
• Ioff Supports Partial-Power-Down Mode Operation
• Max tpd of 1.8 ns at 1.8 V
• ±8-mA Output Drive at 1.8 V
• ESD Protection Exceeds JESD 22
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

简介

SN74AUC2G125属于集成电路（IC）的缓冲器驱动器接收器收发器。由TI制造生产的SN74AUC2G125缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。