SN74AUC16240DGGR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74AUC16240DGGR属于集成电路（IC）的缓冲器驱动器接收器收发器。由美国德州仪器公司制造生产的SN74AUC16240DGGR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

Member of the Texas Instruments

Widebus Family

Optimized for 1.8-V Operation and is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

Ioff Supports Partial-Power-Down Mode

Operation

Sub 1-V Operable

Max tpd of 2 ns at 1.8 V

Low Power Consumption, 20-μA Max ICC

±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This 16-bit buffer/driver is operational at 0.8-V to

2.7-V VCC, but is designed specifically for 1.65-V

to 1.95-V VCC operation.

The SN74AUC16240 is designed specifically to

improve the performance and density of 3-state

memory address drivers, clock drivers, and

bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs

and symmetrical active-low output-enable (OE) inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.