SN74AUC125

具有三态输出的 4 通道、0.8V 至 2.7V 高速缓冲器; • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation\n• Ioff Supports Partial-Power-Down Mode Operation\n• Sub-1-V Operable\n• Max tpd of 2.1 ns at 1.8 V\n• Low Power Consumption, 10-µA Max ICC\n• ±8-mA Output Drive at 1.8 V\n• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II\n• ESD Protection Exceeds JESD 22 \n• 2000-V Human-Body Model (A114-A)\n• 200-V Machine Model (A115-A)\n• 1500-V Charged-Device Model (C101);

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V to 1.95-V VCC operation. The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

SN74AUC125

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AUC125RGYR

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AUC125RGYRG4

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AUC125RGYR

Package：14-VFQFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUFFER NON-INVERT 2.7V 14VQFN

SN74AUC125RGYRG4

Package：14-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUFFER NON-INVERT 2.7V 14VQFN