SN74ALVCH373DGVR集成电路（IC）的锁存器规格书PDF中文资料

SN74ALVCH373DGVR属于集成电路（IC）的锁存器。由德州仪器制造生产的SN74ALVCH373DGVR锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。

FEATURES

· Operates From 1.65 V to 3.6 V

· Max tpd of 3.3 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,

and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When

LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.