SN74ALVCH16973DGGR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74ALVCH16973DGGR属于集成电路（IC）的缓冲器驱动器接收器收发器。由德州仪器制造生产的SN74ALVCH16973DGGR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This device contains four independent noninverting

buffers and an 8-bit noninverting bus transceiver and

D-type latch, designed for 1.65-V to 3.6-V VCC

operation.

The SN74ALVCH16973 is particularly suitable for

demultiplexing an address/data bus into a dedicated

address bus and dedicated data bus. The device is

used where there is asynchronous bidirectional

communication between the A and B data bus, and

the address signals are latched and buffered on the

Q bus. The control-function implementation minimizes

external timing requirements.

This device can be used as one 4-bit buffer, one 8-bit

transceiver, or one 8-bit latch. It allows data

transmission from the A bus to the B bus or from the

B bus to the A bus, depending on the logic level at

the direction-control (DIR) input. The transceiver

output-enable (TOE) input can be used to disable the

transceivers so that the A and B buses effectively are

isolated.