SN74ALVCH162836数据手册集成电路（IC）的通用总线功能规格书PDF

描述 Description

This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE\\) input. The device operates in the transparent mode when the latch-enable (LE\\) input is low. When LE\\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C.

特性 Features

• Member of the Texas Instruments Widebus™ Family
• EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
• Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
• Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesNOTE:For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. Widebus, EPIC are trademarks of Texas Instruments.