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SN74ALVCH16270DLR.B中文资料德州仪器数据手册PDF规格书

SN74ALVCH16270DLR.B
厂商型号

SN74ALVCH16270DLR.B

功能描述

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

丝印标识

ALVCH16270

封装外壳

SSOP

文件大小

275.06 Kbytes

页面数量

15

生产厂商 Texas Instruments
企业简称

TI2德州仪器

中文名称

美国德州仪器公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-6-25 22:59:00

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SN74ALVCH16270DLR.B规格书详情

FEATURES

· Member of the Texas Instruments Widebus™

Family

· EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16270 is used in applications in

which data must be transferred from a narrow

high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate CLKEN inputs are

low. The select (SEL) line selects 1B or 2B data for

the A outputs. For data transfer in the A-to-B

direction, a two-stage pipeline is provided in the

A-to-1B path, with a single storage register in the

A-to-2B path. Proper control of the CLKENA inputs

allows two sequential 12-bit words to be presented

synchronously as a 24-bit word on the B port. Data

flow is controlled by the active-low output enables

(OEA, OEB). The control terminals are registered to

synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as

possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the

outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.

供应商 型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
24+
TSSOP566.1mm
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
TI/德州仪器
24+
NA/
1009
优势代理渠道,原装正品,可全系列订货开增值税票
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TI
23+
TSSOP56
4500
全新原装、诚信经营、公司现货销售!
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TI
23+
TSSOP56
188
原装房间现货假一赔十
询价
TI
2016+
TSSOP
6523
房间原装进口现货假一赔十
询价
TI/德州仪器
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
询价
TI(德州仪器)
2021+
TSSOP-56
499
询价
SN74ALVCH16271DGGR
902
902
询价
TI
2020+
TSSOP
1009
百分百原装正品 真实公司现货库存 本公司只做原装 可
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TEXASINSTRU
24+
原封装
1744
原装现货假一罚十
询价