SN74ALVCH16270集成电路（IC）的通用总线功能规格书PDF中文资料

SN74ALVCH16270属于集成电路（IC）的通用总线功能。由美国德州仪器公司制造生产的SN74ALVCH16270通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16270 is used in applications in

which data must be transferred from a narrow

high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate CLKEN inputs are

low. The select (SEL) line selects 1B or 2B data for

the A outputs. For data transfer in the A-to-B

direction, a two-stage pipeline is provided in the

A-to-1B path, with a single storage register in the

A-to-2B path. Proper control of the CLKENA inputs

allows two sequential 12-bit words to be presented

synchronously as a 24-bit word on the B port. Data

flow is controlled by the active-low output enables

(OEA, OEB). The control terminals are registered to

synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as

possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the

outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.