SN74ALVCH162268DLR集成电路（IC）的通用总线功能规格书PDF中文资料

SN74ALVCH162268DLR属于集成电路（IC）的通用总线功能。由美国德州仪器公司制造生产的SN74ALVCH162268DLR通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Operates From 1.65 V to 3.6 V

· Max tpd of 4.8 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· B-Port Outputs Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162268 is used for applications in

which data must be transferred from a narrow

high-speed bus to a wide, lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate clock-enable

(CLKEN) inputs are low. The select (SEL) line is

synchronous with CLK and selects 1B or 2B input

data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single

storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be

presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables

(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot

and undershoot.