SN74ALVC7804中文资料512 x 18 3.3V 异步 FIFO 存储器数据手册TI规格书

描述 Description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7804 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. The SN74ALVC7804 is designed for 3-V to 3.6-V VCC operation.Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect.Status of the FIFO memory is monitored by the full (), empty (), half-full (HF), and almost- full/almost-empty (AF/AE) flags. Theoutput is low when the memory is full and high when the memory is not full. Theoutput is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable () is low. The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.A low level on the reset () resets the internal stack pointers and setshigh, AF/AE high, HF low, andlow. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up. The first word loaded into empty memory causes to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable () is high.

特性 Features

• Operates at 3-V to 3.6-V VCC
• Load Clock and Unload Clock Can Be Asynchronous or Coincident
• Low-Power Advanced CMOS Technology
• Full, Empty, and Half-Full Flags
• Programmable Almost-Full/Almost-Empty Flag
• Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
• Data Rates From 0 to 40 MHz
• 3-State Outputs
• Pin Compatible With SN74ACT7804
• Packaged in Shrink Small-Outline 300-mil Package (DL) Using 25-mil Center-to-Center Spacing