SN74ALVC162334DGGR集成电路（IC）的通用总线功能规格书PDF中文资料

SN74ALVC162334DGGR属于集成电路（IC）的通用总线功能。由德州仪器制造生产的SN74ALVC162334DGGR通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Ideal for Use in PC100 Register DIMM

· Operates From 1.65 V to 3.6 V

· Max tpd of 3.8 ns at 3.3 V

· ±12-mA Output Drive at 3.3 V

· Output Ports Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· Designed to Comply With JEDEC 168-Pin and

200-Pin SDRAM Buffered DIMM Specification

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit universal bus driver is designed for 1.65-V

to 3.6-V VCC operation.

Data flow from A to Y is controlled by the

output-enable (OE) input. The device operates in the

transparent mode when the latch-enable (LE) input is

low. When LE is high, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If

LE is high, the A data is stored in the latch/flip-flop on

the low-to-high transition of CLK. When OE is high,

the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and

undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.