SN74ALVC125PW集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74ALVC125PW属于集成电路（IC）的缓冲器驱动器接收器收发器。由德州仪器制造生产的SN74ALVC125PW缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

FEATURES

· Operates from 1.65 V to 3.6 V

· Max tpd of 2.8 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Latch-up Performance Exceeds 250 mA Per

JESD 17

· ESD Performance Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.