SNx4AHCT374 Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs

1 Features • Operating range 4.5V to 5.5V VCC • TTL-Compatible inputs • Low delay, 10.5ns (5V VCC at CL = 15pF) • Supports 75MHz • Latch-up performance exceeds 250mA per JESD 17 • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other produc

文件：2.9422 Mbytes 页数：48 Pages

TI

德州仪器

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：233.38 Kbytes 页数：6 Pages

UTC

友顺

Octal D-type flip-flop; positive edge-trigger; 3-state

DESCRIPTION The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：93.09 Kbytes 页数：20 Pages

PHI

飞利浦

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs f

文件：607.89 Kbytes 页数：17 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

DESCRIPTION The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：93.09 Kbytes 页数：20 Pages

PHI

飞利浦