SN74AHCT244MDWREP.A中文资料德州仪器数据手册PDF规格书

Controlled Baseline

– One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

–55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree†

EPIC (Enhanced-Performance Implanted

CMOS) Process

Inputs Are TTL-Voltage Compatible

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 1000 V Per

MIL-STD-833, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

description/ordering information

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state

memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHCT244 is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs.

When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are

in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.